1. Field of the Invention
The present invention relates to a circuit for generating a trim bit signal in NAND type flash memory devices, and more particularly, to a circuit for generating a trim bit signal capable of recovering the trim bit in a package status.
2. Background of the Related Art
In the NAND type flash memory device, the trim bit signal is generated in order to improve and change characteristics of the circuit within the chip.
FIG. 1 illustrates a conventional trim bit block. As shown in FIG. 1, a plurality of trim blocks B1, B2, . . . , Bn are provided. The first trim block B1 outputs a first trim bit signal TBIT1, the second trim block B2 outputs a second trim bit signal TBIT2 and the Nth trim block Bn outputs a Nth trim bit signal TBIT1. Characteristics of the circuit within the chip could be modified or improved by these trim bit signals.
FIG. 2 is a detailed circuit diagram of the trim block shown in FIG. 1. If a fuse FUSE is connected, the input of the inverter INV0 becomes a Low level due to a small current load of the PMOS transistor P0. Therefore, the output of the inverter INV1 becomes a High level, so that the trim bit signal TBIT becomes the High level.
On the contrary, if the fuse FUSE is disconnected, the input of the inverter INV0 becomes a High level. Accordingly, the output of the inverter INV1 becomes a Low level, so that the trim bit signal TBIT becomes the Low level.
In this conventional circuit for generating the trim bit signal, a work for the fuse is performed only in a wafer status. For this reason, the trim bit could not be recovered again after the work is performed. Therefore, there is a disadvantage that the value could not be changed depending on the status after packaging.